The present invention relates to a semiconductor device of a tape ball grid array (BGA) structure, as well as to a method for manufacturing the same.
Recently, as multi-functionalization and high integration of semiconductor integrated circuits are promoted, semiconductor devices further smaller and thinner, with more pins, and further superior in heat radiation have been sought for. Therefore, semiconductor devices called BGAs have been attracting attentions, replacing QFPs (quade flat packages) and TCPs (tape carrier packages).
For example, the Japanese Publications for Laid-Open Patent Applications No. 88245/1996 (Tokukaihei 8-88245, Date of Publication: Apr. 2, 1996), No. 148526/1996 (Tokukaihei 8-148526, Date of Publication: Jun. 7, 1996), and No. 312374/1997 (Tokukaihei 9-312374, Date of Publication: Dec. 2, 1997) disclose BGA packages using TAB (tape automatic bonding) tapes. FIG. 17 shows a tape BGA package disclosed in Tokukaihei 8-88245.
As shown in the same figure, a base film 51 as the TAB tape is provided with through holes 52 and a device hole 53, as well as metal wires 54 on a surface thereof. An inner lead 54a of each metal wire 54 is uncovered in the device hole 53 (the inner lead 54a is formed so as to project from the base film 51), and is subjected to inner lead bonding (ILB) with an electrode 55a of a semiconductor chip 55. A sealing resin 56 is applied thereover, so as to coat an element-formed surface of the semiconductor chip 55 and the inner leads 54a. 
Lands (outer leads) 54b of the metal wires 54 and an external substrate 57 are connected to each other through solder balls 58. Note that the metal wires 54 on the surface of the base film 51, except portions thereof connected with the electrode 55a and portions thereof in contact with the solder balls 58 (hereinafter referred to as solder ball-bonded portions), are covered with a protective film 59. In this manner, the BGA package of a thin film type applicable to a multi-pin structure.
Furthermore, a permeation hole 54c is formed in the land 54b. When the solder ball 58 is provided on the land 54b so as to form a bump, the solder ball 58 creeps up through the permeation hole 54c to the other side. Therefore, it is possible to check the state of soldering by visually checking the state of the creeping up. Furthermore, it is also possible to check electric characteristics, using the creeping up.
However, since the TAB-type BGA package typically arranged as shown in FIG. 17 uses a TAB tape (base film 51) as a substrate, the BGA package, though facilitating the formation of a multiple-port structure and the pitch narrowing, is inferior in coplanarity due to the solder balls 58 arranged on the base film 51 that is flexible, thereby causing non-uniformity in the connection between the metal wires 54 and the external substrate 57 by self-alignment. This results in that disconnection or defective connection occurs, thereby impairing the yield of the packages.
Then, another BGA package has been conventionally proposed, which is, as shown in FIG. 18, arranged as follows: a metal reinforcing plate 66 (equivalent to a stiffener, a lead frame, or the like) in a frame shape which has stiffness is applied on a surface of an insulating tape 61 as a TAB tape, the surface being on a side opposite to the external substrate-connected side. Here, a method for manufacturing a tape BGA package thus arranged is explained below.
First of all, as shown in FIGS. 19(a) and 19(b), inner leads 62a of metal wires 62 on the insulating tape 61 provided with a device hole 61a, and an electrode 63a of a semiconductor chip 63 are subjected to inner lead bonding. On the other hand, a protective film 64 is formed on the metal wire 62 on the insulating tape 61 except a portion thereof connected with the electrode 63a and the solder ball-bonded portions. Then, as shown in FIG. 19(c), a sealing resin 65 is applied from a side of an element-formed surface of the semiconductor chip 63, so as to coat and protect the element-formed surface and the inner leads 62a. 
Next, as shown in FIG. 19(d), the frame-shaped metal reinforcing plate 66 is made to adhere to a back surface of the insulating tape 61 (a surface on a side opposite to the metal wire-formed side). Here, since the inner leads 62a are formed so as to project from the insulating tape 61, if the metal reinforcing plate 66 is attached thereto before the resin sealing, the inner leads 62 are possibly deformed due to stress upon the attachment. To avoid this, the resin sealing is performed before the attachment of the metal reinforcing plate 66 as shown in FIGS. 19(c) and 19(d) so that the inner leads 62 are protected, and thus suppression of deformation of the inner leads 62 is attempted.
Then, as shown in FIG. 19(e), the solder balls 68 for connecting outer leads 62b of the metal wires 62 to an external substrate 67 (see FIG. 18) are formed, thereby ensuring connection between the outer leads 62b and the external substrate 67.
Such device manufacture process is continuously carried out with respect to a tape 69 composed of continuously arranged insulating tapes 61, while the tape 69 is being sent out by reels 60, so that the manufacture process with respect to each insulating tape 61 is continuously carried out. After the metal reinforcing plates 66 are applied, devices are cut out of the tape 69 unit by unit, one unit containing one chip or several chips.
Here, FIG. 21(a) is a plan view of the foregoing tape BGA package obtained by viewing it from the external substrate side (note that the external substrate 67 and the sealing resin 65 are omitted), while FIG. 21(b) is a plan view of the foregoing tape BGA package obtained by viewing it from the metal reinforcing plate 66 side. As shown in FIG. 21(a), a plurality of the solder balls 68 are formed in, for example, a matrix form on the metal wire-formed side of the insulating tape 61, while as shown in FIG. 21(b), the metal reinforcing plate 66 in the frame shape is formed on the back surface of the insulating tape 61.
This arrangement is more or less successful in ensuring coplanarity of the flexible insulating tape 61 and suppressing the warp of the package due to the effect of the metal reinforcing plate 66, and accordingly, possible defects in the electric connection between the metal wires 62 and the external substrate 67 through the solder balls 68 are solved to some extent.
On the other hand, for example, the International Patent Application No. 507344/1997 (Tokuhyohei 9-507344, Date of Publication: Jul. 22, 1997, corresponding to WO96/12298), and the Japanese Publication for Laid-Open Patent Application No. 330994/1997 (Tokukaihei 9-330994, Date of Publication: Dec. 22, 1997) disclose a BGA package of a wire bonding type. As one example of the same, FIG. 22 illustrates a BGA package disclosed by Tokuhyohei 9-507344.
As shown in the same figure, a semiconductor chip 72 is die-bonded to a center recessed part 71a of a lead frame (reinforcing plate) 71 with use of a die bonding paste 73. To the surface of the lead frame 71 except the recessed part 71a, an insulating tape 75 having a conductive pattern 74 such as leads is made to adhere, with adhesive 76. A bump 72a of the semiconductor chip 72 and inner leads 74a of the insulating tape 75 are wire-bonded by a gold wire 77. The semiconductor chip 72 and the gold wire 77 are protected by sealing resin 78. Outer leads 74b and the external substrate 79 are connected to each other through the solder balls 80. Incidentally, the conductive pattern 74 on the surface of the insulating tape 75, except portions thereof connected to the bumps 72a and the solder ball-bonded portions, is coated by the protective film 81.
This arrangement, since having the lead frame 71 on the back surface of the insulating tape 75, enjoys excellent coplanarity and improved electric connection with the external substrate 79.
Incidentally, in the wire bonding type wherein one bump 72a and one inner lead 74a in pair are subjected to wire bonding, terminals necessarily have wider pitch as compared with the TAB type. Therefore, generally, the wire bonding type has inferior to the TAB type in further narrowing the pitch and achieving better multiple-port structure.
However, since the inner lead 62a of the foregoing BGA package is uncovered in the device hole 61a, it tends to deform due to stress or the like during manufacture. As a result, package defects caused by the stress tend to take place, as well.
Besides, as to the TAB-type BGA package typically arranged as shown in FIG. 18, the connection of the electrode 63a of the semiconductor chip 63 with the inner lead 62a, the resin sealing, the attachment of the metal reinforcing plate 66 to the insulating tape 61, the formation of the solder ball 68, the installation of the package on the external substrate 67, and the like are carried out at a high temperature of not lower than 200xc2x0 C. Such a condition of continuous high temperature surely adversely affects the insulating tape 61 and the semiconductor chip 63, thereby leading to package defects.
In the foregoing TAB-type BGA package, however, the metal reinforcing plate 66 which is intended to ensure the coplanarity of the insulating tape 61 seems to have more or less a heat radiating function since being made of a metal, but the heat radiation is possible at limited parts of the surface of the insulating tape 61 since the metal reinforcing plate 66 is disposed only in the vicinity of edges of the insulating tape 61, thereby achieving an extremely poor effect of the heat radiation. As a result, there occur such problems as damages to the insulating tape 61 and package defects, due to influences of heat generated during the manufacture and installation of the package.
On the other hand, in the wire-bonding-type BGA package typically arranged as shown in FIG. 22, the gold wire 77 has to be curved upward (downward in the figure) from the bump 72a, to avoid contact of the gold wire 77 with the semiconductor chip 72. Likewise, the gold wire 77 has to be curved upward (downward in the figure) from the inner lead 74a, to avoid contact of the gold wire 77 with other inner leads 74a. Therefore, as the chip becomes subjected to resin sealing, the resin-sealed portions thereof become thicker as compared with those of the TAB-type package. If the resin-sealed portions become thicker, with solder balls 80 having smaller diameters than a desired one, the resin-sealed portions are caused to come into contact with the external substrate 79, thereby resulting in that the installation of the package on the external substrate 79 becomes difficult. Therefore, it becomes necessary to increase the diameter of the solder balls 80. Consequently, the foregoing arrangement of the BGA package cannot allow the package to be formed thinner and smaller.
The object of the present invention is to provide (1) a semiconductor device of the BGA type which is arranged so as to at least efficiently radiate heat generated during package manufacture as well as to suppress package defects resulting on heat and stress during manufacture, and which is arranged so as to be formed thinner and smaller and to have narrower pitch and a multi-port structure, and (2) a method of manufacturing of such a semiconductor device.
To achieve the foregoing object, a semiconductor device of the present invention is characterized by including (i) a conductive pattern composed of an inner lead section and an outer lead section, the conductive pattern being provided only on an insulating tape, (ii) a plurality of external connection terminals in a protuberance form each, each being connected with the outer lead section at an opening of a protective film, the protective film being formed so as to cover at least the outer lead section of the conductive pattern, (iii) an integrated circuit chip bonded with the inner lead section so that an element-formed surface of the integrated circuit chip faces the insulating tape, and (iv) a first radiating member with a heat radiating property, provided on a surface of the insulating tape on a side opposite to a conductive pattern-formed side thereof so as to cover at least all regions where the external connection terminals are formed.
With the foregoing arrangement in which the inner lead section is formed only on the insulating tape, the inner lead section is never uncovered with the insulating tape. In other words, the inner lead section as a whole is supported by the insulating tape. This ensures that deformation due to stress during manufacture is prevented from easily occurring to the inner lead section, thereby resulting in that package defects resulting on the foregoing stress are prevented.
Furthermore, since the first radiating member is formed on the surface of the insulating tape, it is possible to efficiently and surely emit heat generated during respective steps of the semiconductor device manufacturing process and during the installing step to outside through the first radiating member.
More specifically, in the case of the conventional package equipped with the frame-shaped metal reinforcing plate, an effect of emitting heat of the insulating tape is poor since heat radiation by the metal reinforcing plate is effective only partially with respect to the insulating tape surface. In the foregoing arrangement, however, wherein the first radiating member is formed so as to cover at least all regions where the external connection terminals are formed, the first radiating member has a surface incomparably larger than the metal reinforcing plate, and is capable of surely emitting heat of the entire insulating tape. Moreover, in the case where, for example, another first radiating member is provided at a position vis-a-vis the integrated circuit chip, heat generated during operations of the device can be emitted through the first radiating member.
Thus, the foregoing arrangement produces a remarkably excellent radiating effect as compared with the conventional cases, thereby ensuring that damages to the insulating tape and the integrated circuit chip by heat generated during the manufacturing process and during operations of the device are surely avoided. As a result, package defects resulting on the foregoing heat can be surely reduced.
Furthermore, the integrated circuit chip is connected with the inner lead section formed only on the insulating tape through a pressing operation. This connecting method, which is called as xe2x80x9cflip chip method,xe2x80x9d does not require a metal wire for connecting the integrated circuit chip and the inner lead section which is required in the wire bonding method, and therefore the pitch narrowing and the formation of the multi-port structure are facilitated. Besides, since to form the inner lead sections at narrower spaces on the insulating tape is easier, the foregoing arrangement is particularly effective for the pitch narrowing.
Furthermore, packages formed by the wire bonding method cannot help becoming thick since resin sealing is applied so as to cover the wires, whereas packages formed by the foregoing arrangement are formed thinner as compared with those formed by the wire bonding method, since such wires are unnecessary.
To achieve the aforementioned object, a method for manufacturing the semiconductor device in accordance with the present invention, which is a method for manufacturing a semiconductor device including (i) a conductive pattern composed of an inner lead section and an outer lead section, the conductive pattern being provided only on an insulating tape, and (ii) a plurality of external connection terminals in a protuberance form each, each being connected with the outer lead section through an aperture of a protective film which is formed so as to cover at least the outer lead section of the conductive pattern, (iii) an integrated circuit chip, and (iv) a radiating member which covers at least all regions where the external connection terminals are formed, is characterized by comprising the steps of (a) causing the insulating tape to adhere to the radiating member, with a surface of the insulating tape on a side opposite to a conductive pattern-formed side thereof being in contact with the radiating member, and (b) after the step (a), bonding the integrated circuit chip with the inner lead section so that an element-formed surface of the integrated circuit chip faces the insulating tape.
By the foregoing method, since the conductive pattern is formed only on the insulating tape, the conductive pattern is not prone to deformation in the middle of the manufacturing process. Therefore, the foregoing arrangement allows the step of bonding the insulating tape to the radiating member, which step relatively tends to apply stress on the insulating tape, to be conducted before the step of connecting the integrated circuit chip with the inner lead section; such manufacturing process has conventionally been infeasible since the inner lead section was formed partially outside the insulating tape. Accordingly, the foregoing manufacturing method has become selectable as a method to form the semiconductor device manufacturing method, thereby broadening the range of available manufacturing methods.
Furthermore, unlike a semiconductor device of the TAB type, a step of providing a device hole in the insulating tape for installation of an integrated circuit chip is unnecessary, thereby resulting in that the device manufacturing process is simplified.
To achieve the aforementioned object, another method for manufacturing a semiconductor device in accordance with the present invention, which is a method for manufacturing a semiconductor device including (i) a conductive pattern composed of an inner lead section and an outer lead section, the conductive pattern being provided only on an insulating tape, and (ii) a plurality of external connection terminals in a protuberance form each, each being connected with the outer lead section through an aperture of a protective film, the protective film being formed so as to cover at least the outer lead section of the conductive pattern, (iii) an integrated circuit chip, and (iv) a radiating member which covers at least all regions where the external connection terminals are formed, is characterized by comprising the steps of (a) bonding the integrated circuit chip with the inner lead section so that an element-formed surface of the integrated circuit chip faces the insulating tape, and (b) after the step (a), causing the insulating tape to adhere to the radiating member with a surface of the insulating tape on a side opposite to a conductive pattern-formed side thereof being in contact with the radiating member.
According to the foregoing method, the integrated circuit chip is connected with the inner lead section before the insulating tape is bonded with the radiating member. Therefore, it is possible to perform the integrated circuit chip-inner lead section bonding step with respect to a plurality of chips simultaneously, by using a tape in which insulating tapes for a plurality of chips are continuously formed. This method enables improvement of the throughput of the semiconductor device.
Furthermore, unlike a semiconductor device of the TAB type, a step of providing a device hole in the insulating tape for installation of an integrated circuit chip is unnecessary, thereby resulting in that the device manufacturing process is simplified.
To achieve the aforementioned object, still another method for manufacturing a semiconductor device in accordance with the present invention is characterized by including the steps of (a) forming a lead frame including a plurality of radiating regions formed so as to cover at least all regions where a plurality of external connection terminals each in a protuberance form are provided, (b) causing an insulating tape having a conductive pattern thereon to adhere to each radiating region, with a surface of the insulating tape on a side opposite to a conductive pattern formed-surface being in contact with the radiating region, the conductive pattern of the insulating tape being composed of an inner lead section and an outer lead section, the insulating tape having a protective film covering at least the outer lead section, (c) bonding the integrated circuit chip with the inner lead section so that an element-formed surface of the integrated circuit chip faces the insulating tape, (d) connecting each external connection terminal in the protuberance form with the outer lead section through an aperture of the protective film, and (e) cutting the lead frame so that the radiating regions are separated from each other.
According to the foregoing arrangement, the conductive pattern is formed only on the insulating tape, hence the conductive pattern is not prone to deformation in the middle of the manufacturing process. Therefore, the foregoing arrangement allows the step of bonding the insulating tape to the radiating member, which step relatively tends to apply stress on the insulating tape, to be conducted before the step of connecting the integrated circuit chip with the inner lead section; such manufacturing process has conventionally been infeasible since the inner lead section was formed partially outside the insulating tape. Accordingly, the foregoing manufacturing method has become selectable as a method to form the semiconductor device manufacturing method, thereby broadening the range of available manufacturing methods.
Furthermore, according to the foregoing method, a plurality of chips are simultaneously formed using a lead frame having a plurality of radiating regions, thereby resulting in that the throughput of the semiconductor device is improved as compared with the other aforementioned methods.
Furthermore, unlike a semiconductor device of the TAB type, a step of providing a device hole in the insulating tape for installation of an integrated circuit chip is unnecessary, thereby resulting in that the device manufacturing process is simplified.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.